Run-time generation of partial FPGA configurations
نویسندگان
چکیده
منابع مشابه
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increased functionality. Even though recent advances in Xilinx’s Virtex-4 and Virtex-5 FPGA devices and design tools significantly improve the practicality of incorporating PR, unfortunately, system designers largely lack su...
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Although the new generations of FPGAs provide support for partial and dynamic configuration, the huge reconfiguration latency is still a major shortcoming of the current FCCMs . Software and hardware techniques (compiler optimizations, configuration prefetching) have been used in order to reduce the impact of the configuration overhead on the overall performance. Nevertheless, these techniques ...
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In this paper a temperature sensor for FPGAs that can be dynamically inserted and eliminated from the circuit is presented. Using run-time reconfiguration, a ringoscillator together with its auxiliary circuitry (counting and control stages) is inserted in the design. After the actual temperature of the die is captured, the value is read back and the sensor is eliminated from the FPGA. This avoi...
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ژورنال
عنوان ژورنال: Journal of Systems Architecture
سال: 2012
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2011.10.001